Event Detail
Title: Timing Closure: Requirements for Variation Aware Design - Presented by Extreme DA / TI / PDF Solutions / UMC
Type: HOT
Track: DFM and the Manufacturing Interface
Day:
Thursday
Time: 9:00 AM - 12:00 PM
Room: 11A
Abstract: Scaling of the designs leads to the emergence of new physical challenges that limit continuing improvement of circuit performance. Among them, statistical process and environmental variations have caused headache to designers. In previous silicon generations, conservative margins could be afforded to guard-band against these uncertainties. However at the technologies nodes of 65nm and below, more realistic analysis is needed to deliver silicon that meets yield and performance goals.In this tutorial, the audience will be introduced to the components of a next generation timing analysis methodology. We show practical examples starting from front-end and back-end process characterization that captures variability statistics of systematic and random variations.Experiences from Foundry, IDM, and EDA perspectives will be covered. The use of the extracted variability data in the library characterization, RC extraction, timing analysis and optimization flows will be demonstrated.
