Event Detail
Title: Deploying Statistical Timing -- from Characterization to Analysis and Optimization - Presented by Altos / Cadence
Type: HOT
Track: DFM and the Manufacturing Interface
Day:
Tuesday
Time: 2:00 PM - 5:00 PM
Room: 11A
Abstract: Statistical static timing analysis (SSTA) offers a number of advantages over traditional corner based static timing analysis (STA), most notably it provides a more realistic estimation of timing relative to actual silicon performance. Armed with a better answer, designers can focus their optimization efforts on the paths that have the biggest impact on overall performance resulting in improved yield, reduced power (especially leakage) and shorter design cycles. In addition, STA may miss chip failures due to process variations that SSTA will be able to pin-point. This hands-on tutorial will show how to incorporate SSTA into your existing design methodology.The tutorial will contrast the results of performing analysis and optimization using both STA and SSTA on a provided design. The attendees will also learn how to easily and efficiently characterize a statistical timing library that accounts for process variations.The attendees will walk away with practical experience of the complete SSTA design methodology and a detailed understanding of its key advantages.
