Event Detail
Session: 50:Mixed-Signal Modeling, Methodology and Synthesis
Type: Regular Session
Track: Analog/Mixed-Signal/RF and Simulation
Day:
Thursday
Time: 4:30 PM - 6:00 PM
Room: 6D
Chair: Puneet Gupta - UC
50.1 Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits, X. Li, L. Pileggi - CMU
50.2 Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop, K. Kang, K. Kim, K. Roy - Purdue
50.3s Parameterized Macromodeling for Analog System-Level Design Exploration, J. Wang, X. Li, L. Pileggi - CMU
50.4s Simultaneous Multi-Topology Multi-Objective Circuit Sizing Across Thousands of Analog Circuit Topologies, T. Mcconaghy, P. Palmers, G. Gielen, M. Steyaert - Katholieke Univ.
Abstract: Going to the system level while considering the impact of process technology is a key issue in today's mixed-signal design. This sessions presents new ideas to deal with this challenge. The first paper presents a new way to estimate yield, inspired by advances in statistical timing analysis. The second paper deals with built-in compensation of process variations. The third paper presents a new divide&conquer approach to response surface modeling for analog blocks. The fourth paper finally shows an integrated approach to structural and parametric analog synthesis.
