Event Detail
Session: 49:FPGA Tools and Methodologies
Type: Regular Session
Track: Synthesis and FPGA
Day:
Thursday
Time: 4:30 PM - 6:00 PM
Room: 6C
Chair: Xiaojian Yang - Synplicity, Inc.
49.1 DDBDD: Delay-Driven BDD Synthesis for FPGAs, L. Cheng, D. Chen, M. Wong - U. Illinois
49.2 An High-End Realtime Stream Processing Library for FPGAs, A. Lucas, S. Heithecker, R. Ernst - Technical Univ. of Braunschweig
49.3 How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs, C. Zhou, W. Tang, W. Lo
Abstract: This session focuses on new improvements in FPGA synthesis at system and logic level. The first paper introduces a new BDD synthesis approach using linear BDD expansion considering delay as a parameter when searching for cuts. The second paper proposes a general tool flow targeting high throughput video processing applications. The third paper considers rewiring to reduce area and delay.
