Event Detail
Session: 46:Technology Mapping and Physical Synthesis
Type: Regular Session
Track: Synthesis and FPGA
Day:
Thursday
Time: 2:00 PM - 4:00 PM
Room: 6F
Chair: Mahesh Iyer - Synopsys
46.1 A Unified Approach to Canonical Form-based Boolean Matching, G. Agosta, F. Bruschi, G. Pelosi, D. Sciuto - Politecnico di Milano
46.2 Gate Sizing For Cell Library-Based Designs, S. Hu - Texas A&M, College Station, M. Ketkar - Intel, J. Hu - Texas A&M
46.3 Statistical Leakage Power Minimization Using Fast Equi-Slack Shell Based Optimization, X. Ye - Texas A&M
46.4 Techniques for Effective Distributed Physical Synthesis, W. Hou, F. Mang, P. Ho - Synopsys
Abstract: This section focuses on technology mapping and physical synthesis. The first three papers address various aspects of technology mapping and the last paper merges physical design and logic synthesis.
