Event Detail
Session: 45:Modeling Technology Impact
Type: Regular Session
Track: DFM and the Manufacturing Interface
Day:
Thursday
Time: 2:00 PM - 4:00 PM
Room: 6E
Chair: D. Pandini - STMicroelectronics
45.1 A General Framework for Spatial Correlation Modeling in VLSI Design, F. Liu - IBM
45.2 Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation, R. Singhal, A. Balijepalli, A. Subramaniam, F. Liu, S. Nassif - IBM, Y. Cao - ASU
45.3 A Framework for Accounting for Process Model Uncertainty in Statistical Static Timing Analysis, W. Dong, G. Yu, Z. Feng, P. Li - Texas A&M
45.4 Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method, Y. Zhou - Texas A&M, Z. Li - Pextra Corp., W. Shi - Texas A&M
Abstract: With technology scaling, the interaction between design practice (circuit and layout) and performance and algorithms is becoming more complex. This session includes a number of papers that examine this interaction at the device, layout, and interconnect levels.
