Event Detail
Session: 44:Embedded Processor and MPSoC Design
Type: Regular Session
Track: System Level and Embedded
Day:
Thursday
Time: 2:00 PM - 4:00 PM
Room: 6D
Chair: Nikil Dutt - UC
44.1 RISPP: Rotating Instruction Set Processing Platform, L. Bauer, M. Shafique, S. Kramer, J. Henkel - Univ. of Karlsruhe
44.2s ASIP Instruction Encoding for Energy and Area Reduction, P. Morgan, R. Taylor - Critical Blue
44.3s Approximation Algorithm for Data Mapping on Block Multi-threaded Network Processor Architectures, C. Ostler, K. aram S. Chatha - Arizona S
44.4 Program Mapping onto Network Processors by Recursive Bipartitioning and Refining, J. Yu - U. Pittsburgh, J. Yao, L. Bhuyan - UC, J. Yang - U. Pittsburgh
44.5 Design Methodology for Pipelined Heterogeneous Multiprocessor System, S. Shee, S. Parameswaran - Univ. of New South Wales
Abstract: The session presents exciting new system-level design challenges targeting diverse platforms ranging from low-end energy and area-constrained processors to very high-end performance-driven many-core network and multimedia processors. Papers address topics ranging from novel instruction encodings for extensible/configurable processors, application mapping approaches on state-of-the-art network processors, and architecture design of pipelined multimedia MPSoCs.
