Event Detail
Session: 43:Communication-Based Resource Allocation
Type: Regular Session
Track: Synthesis and FPGA
Day:
Thursday
Time: 2:00 PM - 4:00 PM
Room: 6C
Chair: Luca Carloni - Columbia
43.1 Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture, K. Lim, Y. Kim, T. Kim - Seoul National Univ.
43.2 Selective Bandwidth and Resource Management in Scheduling for Dynamically Reconfigurable Architectures, S. Banerjee, E. Bozorgzadeh - UC, J. Noguera - Technical Univ. of Catalonia, N. Dutt - UC
43.3 Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs, S. Stuijk, T. Basten, M. Geilen,
43.4s Global Critical Path: A Tool for System-Level Timing Analysis, G. Venkataramani - CMU, M. Budiu - Microsoft Corp., T. Chelcea, S. Goldstein - CMU
43.5s Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification, P. Chandraiah, R. Doemer - UC
Abstract: This session's papers consider communication issues to generate better designs. This principle is applied across a broad range of abstraction levels: microarchitectural, reconfigurable and multiprocessor, to produce improved results. The final two short papers describe novel tools that help guide designers towards better designs.
