Event Detail
Session: 42:SPECIAL SESSION: Thousand-Core Chips
Type: Special Session
Track: System Level and Embedded
Day:
Thursday
Time: 2:00 PM - 4:00 PM
Room: 6B
Chair: David Yeh - TI
42.1 Thousand-Core Chips - A Technology Perspective, S. Borkar- Intel
42.2 The Kill Rule for Multicore, A. Agarwal - Massachusetts Institute of Tech.
42.3 Sequential Programming Models for Programming Thousand-Core Systems, W. Hwu, S. Ryoo, S. Ueng, J.H. Kelm - U. Illinois, Urbana, I. Gelado - Universitat Politecnica de Catalunya,
S. Stone, R. Kidd, S. Baghsorkhi, A. Mahesri, S. Tsao, Nacho Navarro - Universitat Politecnica de Catalunya (UPC. Lumetta, M. Frank, S. Patel - U. Illinois, Urbana, IL
42.4 Multi-Core Design Automation Challenges, J. Darringer - IBM
Abstract: While there is wide consensus that future chips will be multi-core, will industry ever scale to thousand-core chips? This special session examines this important question from four perspectives: technology, architecture, programming, and design automation. There is no debate that we have sufficient raw transistors. But, what will the power characteristics be? How will the cores be interconnected on and off-chip? How do we size the core cache? How will we program such chips while dealing with legacy software? How can EDA mitigate design, testing and verification complexity? These are just some of the issues the speakers will address as they pave the way for thousand-core chips.
