Event Detail
Session: 38:Emerging Test Solutions
Type: Regular Session
Track: Verification and Test
Day:
Thursday
Time: 9:00 AM - 11:00 AM
Room: 6D
Chair: A. Orailoglu - UC San Diego
38.1 A Robust Protocol for Concurrent On-Line Test (COLT) of NoC-based Systems-on-a-Chip, P. Bhojwani, R. Mahapatra - Texas A&M
38.2 SoC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects, Q. Xu, Y. Zhang - The Chinese U. of Hong Kong, K. Chakrabarty - Duke Univ.
38.3 A DFT Method for Time Expansion Model at Register Transfer Level, H. Iwata, T. Yoneda, H. Fujiwara - Nara Institute of Science & Tech.
38.4 Test Generation in the Presence of Timing Exceptions and Constraints, K. Tsai, D. Goswami, M. Kassab, J. Rajski - Mentor
Abstract: This session provides wide aspects of test technologies for emerging test problems. The first two papers address SoC test problems, the third paper proposes a new RTL DFT methodology, and the fourth paper treats an at-speed overtesting problem.
