Event Detail
Session: 34:3D IC and Package Design Issues
Type: Regular Session
Track: Physical Design
Day:
Wednesday
Time: 4:30 PM - 6:30 PM
Room: 6F
Chair: John Berrie - Zuken UK Ltd.
34.1 An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design, J. Fang, C. Hsu, Y. Chang - Nat'l Taiwan U.
34.2 Computationally Efficient Power Integrity Simulation for System-on-Package Applications, K. Bharath, E. Engin, M. Swaminathan, - Georgia Institute of Tech., K. Uriu, T. Yamada - Matsushita Electric Industrial Co., Ltd.
34.3s Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design, H. Yu - Berkeley Design Automation, C. Chu, L. He - UC
34.4s Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors, K. Puttaswamy, G. Loh - Georgia Institute of Tech.
34.5 Placement of 3D ICs with Thermal and Interlayer Via Considerations, B. Goplen, S. Sapatnekar - Univ. of Minnesota
Abstract: This session covers design beyond the boundaries of the chip die, including the hot topics of 3-D IC design and system-in-package. Innovative approaches are presented in important areas where technology is developing rapidly.
