Event Detail
Session: 32:SPECIAL SESSION: The Future of Interconnects: How Will Billions of Transistors Communicate in the Nanometer Era
Type: Special Session
Track: Interconnect and Reliability
Day:
Wednesday
Time: 4:30 PM - 6:30 PM
Room: 6C
Chair: Nagaraj NS - TI
32.1 Interconnects in the 3rd Dimension: Design and Process Challenges for 3D Ics, K. Bernstein, P. Andry, J. Cann, P. Emma, D. Greenberg, W. Haeson, M. Ignatowski, S. Koester, J. Macerlein, R. Puri
32.2 Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects, A. Naeemi, R. Sarvari, J. Meindl - Georgia Institute of Tech.
32.3 Micro-Photonic Interconnects: Characteristics, Possibilities and Limitations, J. Roychowdhury - Univ. of Minnesota
32.4 CAD Implications of New Interconnect Technologies, L. Scheffer - Cadence
Abstract: In nanometer era, interconnects have become the primary limiter of performance, energy dissipation, and signal integrity in complex IC designs. In next decade, CMOS technology will enable billions of transistors on a chip, which will impose unprecedented challenges on the interconnects in terms of bandwidth and power requirements. To address these challenges, a broad spectrum of novel solutions to the multifaceted interconnect problem must be explored. A failure to meet these challenges threatens to derail the progress of chip and system designs of the future. This special session will include presentations from world renowned experts in industry and academia to address these challenges by focusing on all three aspects of this crucial problem: technology; design; and CAD. Presentations will address issues ranging from: Interconnects in 3rd dimensions - design and process challenges for 3D ICs; performance modeling and optimization challenges of carbon nanotube interconnects; characteristics, possibilities, and limitations of micro-photonic interconnects; and modeling simulation and CAD needs of future interconnects.
