Event Detail
Session: 30:Practical Solutions for Power-Aware Testing
Type: Regular Session
Track: Verification and Test
Day:
Wednesday
Time: 2:00 PM - 4:00 PM
Room: 6A
Chair: Sandip Kundu - Univ. of Massachusetts
30.1 Scan Test Planning for Power Reduction, M. Imhof, C. Zoellin, H. Wunderlich - Universitaet Stuttgart, N. Maeding, J. Leenstra - IBM
30.2 Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing, X. Wen - Kyushu Institute of Tech., K. Miyase - Japan Science & Tech. Agency, T. Suzuki, S. Kajihara - Kyushu Institute of Tech., Y. Ohsumi - Dai Nippon Printing, Co., K. Saluja - Univ. of Wisconsin
30.3 Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SoC Design, N. Ahmed, M. Tehranipoor - Univ. of Connecticut, V. Jayaram - Texas Instruments, Inc.
30.4 New Test Data Decompressor for Low Power Applications, D. Czysz - Poznan Univ. of Technology, G. Mrugalski, J. Rajski - Mentor., J. Tyszer - Poznan Univ. of Technology
Abstract: This session proposes various complementary solutions for addressing the problem of excessive power consumption during test. The first paper presents an automated solution for the generation of power-aware scan test planning. The next two papers address the problem of power-constrained test pattern generation for at-speed testing. The last one presents a low-power test data compression scheme.
