Event Detail
Session: 28:Advances in Embedded Hardware Design
Type: Regular Session
Track: System Level and Embedded
Day:
Wednesday
Time: 2:00 PM - 4:00 PM
Room: 6E
Chair: Tony Givargis - UC
28.1 Modeling the Function Cache for Worst-Case Execution Time Analysis, R. Kirner, M. Schoeberl - Vienna Univ. of Tech.
28.2 An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration, C. Kao, I. Huang, C. Lin - National Sun Yat-Sen Univ.
28.3 Hardware Support for Secure Processing in Embedded Systems, S. Mao, T. Wolf - Univ. of Massach
28.4s RIJID: Random Code Injection to Mask Power Analysis Based Side Channel Attacks, J. Ambrose, R. Ragel, S. Parameswaran - Univ. of New South Wales
28.5s Compact State Machines for High Performance Pattern Matching, P. Piyachon, Y. Luo - Univ. of Massachusetts
Abstract: This session presents various topics in the area of embedded hardware design. The first paper describes a WCET cache analysis approach. Next a novel multi-resolution bus tracer is described folowed by two papers dealing with security extensions to embedded processors. Finally an efficient pattern matching approach in hardware is presented.
