Event Detail
Session: 22:SPECIAL SESSION: Silicon Measurement Correlation to Reliability, Noise and Timing Effects
Type: Special Session
Track: DFM and the Manufacturing Interface
Day:
Wednesday
Time: 10:30 AM - 12:00 PM
Room: 6C
Chair: Yu (Kevin) Cao - Arizona State Univ.
22.1 Design-Silicon Timing Correlation - A Data Mining Perspective, L. Wang, P. Bastani - UC, M. Abadir - Freescale
22.2 Silicon Speedpath Measurement and Feedback into EDA Flows, K. Killpack, C. Kashyap, E. Chiprout - Intel
23.3s Characterizing Process Variation in Nanometer CMOS, K. Agarwal, S. Nassif - IBM
22.4s On-Chip Measurements Complementary to Design Flows for Integrity in SoCs, M. Nagata - Kobe Univ.
Abstract: Industrial and academic speakers on the advanced line of EDA research will focus on a newly highlighted area of silicon sampling approaches as well as CAD algorithms and methodologies required to feed silicon measurements back into EDA tools and flows and to correlate the data to the underlying models and algorithms in order to reduce design pessimism by improving silicon prediction.The EDA community has historically created diverse models and algorithms for effects in timing, signal integrity, and reliability. Each of these models typically considers one or two effects which are solved in isolation. However, in silicon, the "real deal" happens where the impact of power droop, cross-coupling noise, MIS, degradation and other timing , noise and reliability effects occur at the same time and are highly correlated. The actual silicon effects need to be understood and correlated to the developing models and algorithms.
