Event Detail
Session: 19:Process Aware Physical Design
Type: Regular Session
Track: Physical Design
Day:
Wednesday
Time: 8:30 AM - 10:00 AM
Room: 6F
Chair: Lars Liebmann - IBM
19.1 Fast Min-Cost Buffer Insertion under Process Variations, R. Chen, H. Zhou - Northwestern
19.2 Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks, B. Taylor, L. Pileggi - CMU
19.3s Concurrent Wire Spreading, Widening and Filling, O. Rizzo, H. Melzner - Infineon T
19.4s Modeling Litho-Constrained Design Layout, M. Tsai, D. Zhang, Z. Tang - Synopsys
Abstract: Modern physical design must be aware of the nanometer technology effects such as lithography, variability and random defect yield. Two papers optimized cells and wiring for lithography constraints, one adjusts the wiring to maximize defect limited yield, and the remaining paper addresses buffer insertion considering process variation.
