Event Detail
Session: 18:Physical Implementation of FPGAs
Type: Regular Session
Track: Synthesis and FPGA
Day:
Wednesday
Time: 8:30 AM - 10:00 AM
Room: 6E
Chair: Tim Tuan - Xilinx, Inc.
18.1 GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches, L. Cheng, D. Chen, M. Wong - U. Illinois
18.2 Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits, T. Czajkowski, S. Brown - Univ. of Toronto
18.3 Single-Event-Upset (SEU) Awareness in FPGA Routing, S. Golshan, E. Bozorgzadeh - UC
18.4s Enhancing FPGA Performance for Arithmetic Circuits, P. Brisk, A. Verma - EPFL, H. Parandeh-Afshar - Univ. of Tehran, P. Ienne - EPFL
Abstract: Physical effects plague modern and future FPGA architectures. Glitches and soft errors are commonplace and will become more so in the future. The first three papers provide techniques to mitigate glitches and soft errors. The final paper describes a novel architecture feature to enhance arithmetic operations.
