Event Detail
Session: 12:PANEL: Early Power-Aware Design and Validation: Myth or Reality?
Type: Panel
Track: Low Power Design
Day:
Tuesday
Time: 4:30 PM - 6:30 PM
Room: 6C
Chair: S. Bailey - Mentor
Organizers: G. Kamhi - Intel, S. Miller - ThinkBold
Speakers: 12.1 Early Power-Aware Design and Validation: Myth or Reality?, S. Curtis - Intel, J. Karmann - Infineon, S. Kosonocky - IBM, E. Macii - Politecnico di Torino, W. Nebel - OFFIS Research Institute, YC Wong - Broadcom
Abstract: Design for low power is crucial for developing and optimizing complex SoCs. Typically, power issues are tackled at the gate-level and backend stages, disconnected from microarchitectural power features or RTL . Industry leaders will debate whether early power-aware design and validation is viable, and which stage of the design process is best for dealing with power issues: gate level and below, or system level.
