Event Detail
Session: 10:Signal and Power Delivery Integrity
Type: Regular Session
Track: Interconnect and Reliability
Day:
Tuesday
Time: 2:00 PM - 4:00 PM
Room: 6F
Chair: Eli Chiprout - Intel
10.1 On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise, M. Zhao, R. Panda, B. Reschke, Y. Fu - Freescale, T. Mewett - Australia Semiconductor, S. Chandraskearan, S. Sundareswaran, S. Yan - Freescale
10.2 Optimal Selection of Voltage Regulator Modules in a Power Delivery Network, B. Amelifard, M. Pedram - USC
10.3 Top-k Aggressors Sets in Delay Noise Analysis, R. Gandikota, K. Chopra
10.4s A New Twisted Differential Line Structure in Global Bus Design, Z. Jiang, S. Hu, W. Shi - Texas A&M
10.5s Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew, A. Roy, N. Mahmoud, M. Chowdhury - U. Illinois
Abstract: This session deals with noise and reliability issues in signal and power lines. The first paper presents a technique that simultaneously sizes power wires and adds decaps. The second paper presents a new hierarchical methodology for multi-level on-chip voltage conversion. The third paper deals with the effects of signal integrity on timing analysis. The fourth paper presents a more practical approach for twisted bundle interconnect. The last paper addresses the effects of inductive coupling on delay uncertainty and clock skew.
