Event Detail
Title: Low Power Coalition Workshop - Standards for Low Power Design Intent
Type: Workshop
Track: Low Power Design
Day:
Sunday
Time: 12:30 PM - 3:30 PM
Room: 6D
Organizers: Bill Bayer, S. DasGupta, N. English - Si2
Speakers: G. Watt - AMD, Q. Wang - Cadence, G. Delp - LSI, R. Aitken - ARM, H. Menager - NXP, T. Miller - Sequence, D. Varma - Calypto, D. Allen - Atrenta, A. Iyer - ArchPro
Abstract: Low-power requirements are a primary concern for IC designs across all product categories. They affect all electronic systems, all of which are experiencing intense pressure to reduce power consumption. For the IC design process, several advanced techniques have emerged to reduce power consumption in SoCs including the use of multiple power domains, multiple supply voltages, dynamic and adaptive voltage and frequency scaling, and task-dependent power shut-off. However, these new techniques impose new requirements on existing design libraries, tools and methodologies. The Low Power Coalition is developing new approaches to help specify, manage and communicate power-related information and constraints consistently throughout the design flow. One of the first actions of the LPC was the issuance of the Common Power Format specification. CPF captures low power design intent so that it can be used to consistently communicate low power constraints throughout the IC design flow. This workshop will cover some of the recent activity and planned roadmap of the LPC.
