Event Detail
Title: Design and Verification of Low Power Ics
Type: Workshop
Track: Low Power Design
Day:
Sunday
Time: 4:00 PM - 7:00 PM
Room: 6E
Organizers: K. Bartleson - Synopsys
Moderator: Y. Trivedi - Magma
Speakers: Y. Trivedi - Magma, D. Peterman - TI, S. Mehta - Sun, E. Rashba - IEEE, S. Bailey - Mentor, G. Delp - LSI, M. Keating - Synopsys, J. Karmann - Infineon
Abstract: Power management is critical in IC design, especially for mobile devices, battery-operated systems, and non-portable systems with power consumption constraints. For an interoperable, multi-vendor tool flow for low-power design and verification, the IEEE is producing a standard based on the Unified Power Format (UPF) and other contributions. UPF is language-independent and comprehensive, specifying power-aware requirements, design intent, implementation, verification and analysis. UPF became an Accellera standard in February 2007, and EDA vendors are actively developing tool support. The IEEE process began in February, using its entity-based model for market-relevant standards. In this workshop, experts will provide everything an engineer or tool developer needs to use UPF today (with an eye towards the IEEE standard) including its purpose, technical constructs and usage. Leading EDA suppliers will show interoperability in a multi-vendor flow. Attendees will be well-equipped to leverage UPF today -- and the future IEEE standard -- to meet their low-power IC challenges.
