Event Detail
Session: 5:Formal and Semi-Formal Verification Techniques
Type: Regular Session
Track: Verification and Test
Day:
Tuesday
Time: 10:30 AM - 12:00 PM
Room: 6F
Chair: Magdy S. Abadir - Freescale Semiconductor Inc.
5.1 An Effective Guidance Strategy for Abstraction-Guided Simulation, F. Paula, A. Hu - Univ. of British Columbia
5.2 Leveraging Semi Formal and Sequential Equivalence Techniques for Multimedia SoC Performance Validation, L. Bhatia, J. Gaur, P. Tiwari, R. Mitra, S. Matange - TI
5.3 Synthesizing SVA Local Variables for Formal Verification, J. Long, A. Seawright - Mentor.
Abstract: This session hosts papers presenting advances in blending formal, semi-formal, and dynamic techniques for validation. The first paper presents a strategy for using formal engines to guide simulation. The second paper bring formal and semi-formal techniques to performance, rather than functional, validation. The last paper highlights challenges in handling local variables efficiently in the SVA-to-formal path.
