Event Detail
Session: 4:Novel Techniques for Interconnect
Type: Regular Session
Track: Interconnect and Reliability
Day:
Tuesday
Time: 10:30 AM - 12:00 PM
Room: 6E
Chair: Jiang Hu - Texas A&M
4.1 Design of Rotary Clock Based Circuits, Z. Yu, X. Liu - North Carolina State Univ.
4.2 Escape Routing For Dense Pin Clusters In Integrated Circuits, M. Ozdal - Intel
4.3s TROY: Track Router with Yield-driven Wire Planning, M. Cho - Univ. of Texas
4.4s IPR: An Integrated Placement and Routing Algorithm, M. Pan - Cadence, C. Chong-Nuen Chu - Iowa State Univ.
Abstract: This session presents solutions to various interconnect-related issues. The first paper illustrates how a novel clocking scheme can be applied to real-life chip design.The following paper addresses routability and runtime by pre-routing dense pins using a multi-commodity flow formulation. A yield-driven track routing methodology is presented in the third paper. The final paper presents an original approach to feeding back routing congestion into placement.
