Event Detail
Title: Accellera Breakfast and Panel Discussion
Type: Meeting
Track: Business
Day:
Wednesday
Time: 7:30 AM - 9:30 AM
Room: 26AB
Organizers: K. Silver - Denali
Abstract: The lunch panel topic is: "IP, SystemVerilog’s Final Frontier." The industry asked for SystemVerilog, and Accellera delivered. With support from leading EDA vendors, and the leadership of Accellera's member representatives in the design and verification community, SystemVerilog is now being successfully deployed across the industry. Early adopters are already reaping the rewards of using SystemVerilog for functional verification, but what about the application of SystemVerilog to design and integration of IP for SoC design? Panelists representing commercial IP providers, EDA vendors, and IP consumers will address real world benefits of SystemVerilog in the IP domain, and examine state-of-the art flows for IP design and integration, which is next frontier for SystemVerilog. This panel is sponsored by Denali Software, and is open to all DAC attendees.
