Exh S M Tu W Th F #

Session: PANEL: Megatrends and EDA 2017
Type: Panel
Track: Business
Day:  Tuesday
Time: 10:30 AM - 12:00 PM
Room: 6C
Chair: G. Spirakis - retired Intel, currently Board Member at ArchPro
Organizers: F. Bacchini - Francine Bacchini, Inc.
Speakers: 2.1 Megatrends and EDA 2017, J. Carballo - Argon Capital, A. de Geus - Synopsys, F. Hsu - TSMC, K. Keutzer - UC Berkeley, K. Yamada - NEC, View Detail

Session: SPECIAL SESSION: Trusted Hardware
Type: Special Session
Track: Interconnect and Reliability
Day:  Tuesday
Time: 10:30 AM - 12:00 PM
Room: 6B
Chair: P. Schaumont - Virginia Polytechnic Inst.
1.1s Challenges for Trusted Hardware, K. Levitt - NSF1.2s Trusted Design in FPGAs, 
1.3  Physical Unclonable Functions for Device Authentification and Secret Key Generation, 
Side Channel Attack Pitfalls,  View Detail

Title: Tutorial #3 - Formal Assertion Based Verification in an Industrial Setting
Type: Friday Tutorial
Track: Verification and Test
Day:  Friday
Time: 9:00 AM - 5:00 PM
Room: 6F
Session Title: Tutorial #3 - Formal Assertion Based Verification in an Industrial Setting
Organizers: R. Mitra - TI
Speakers: A. Jain - Cadence, R. Mitra - TI, J. Baumgartner - IBM, P. Dasgupta - Indian Institute of Tech., View Detail

Title: Design without Borders -- A Tribute to the Legacy of A. Richard Newton
Type: Keynote
Track: New and Emerging Technologies
Day:  Thursday
Time: 12:30 PM - 1:45 PM
Room: 20ABC
Session Title: Design without Borders -- A Tribute to the Legacy of A. Richard Newton
Speakers: Jan M. Rabaey - Donald O. Pederson Distinguished Professor, Director Gigascale Systems Research Center (GSRC), Scientific Co-director BWRC, UC Berkeley, View Detail

Type: Pavillion Panel
Track: Business
Day:  Monday
Time: 4:15 PM - 5:00 PM
Room: Booth 6360
Organizers: Jill O. Williams
Moderator: Ed Sperling - Electronic News , San Jose, CA
Moderator: Ed Sperling - Electronic News , San Jose, CA
Speakers: I. Drew - ARM Ltd, E. Valdez - Parrot SA, View Detail

Title: IEEE Council on EDA's Distinguished Speaker Lecture and Reception
Type: Adjunct
Day:  Monday
Time: 6:00 PM - 8:00 PM
Room: Sails Pavilion
Session Title: IEEE Council on EDA's Distinguished Speaker Lecture and Reception
View Detail

Session: Industrial Application of System Level Methods
Title: IEEE Council on EDA’s Distinguished Speaker Lecture and Reception
Type: Regular Session
Track: System Level and Embedded
Day:  Tuesday
Time: 10:30 AM - 12:00 PM
Room: 6D
Session Title: IEEE Council on EDA’s Distinguished Speaker Lecture and Reception
Chair: Grant Martin - Tensilica Inc.
3.1 System-Level Design Flow Based on a Functional Reference for HW and SW, W. Tibboel, V. Reyes, M. Klompstra, D. Alders - NXP Semiconductors3.2 Model-Driven Validation of SystemC Designs, 
3.3s Language Extensions to SystemC: Process Control Constructs, 
Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264,  View Detail

Session: Novel Techniques for Interconnect
Type: Regular Session
Track: Interconnect and Reliability
Day:  Tuesday
Time: 10:30 AM - 12:00 PM
Room: 6E
Chair: Jiang Hu - Texas A&M
4.1 Design of Rotary Clock Based Circuits, Z. Yu, X. Liu - North Carolina State Univ.4.2 Escape Routing For Dense Pin Clusters In Integrated Circuits, 
4.3s TROY: Track Router with Yield-driven Wire Planning, 
IPR: An Integrated Placement and Routing Algorithm,  View Detail

Session: Formal and Semi-Formal Verification Techniques
Type: Regular Session
Track: Verification and Test
Day:  Tuesday
Time: 10:30 AM - 12:00 PM
Room: 6F
Chair: Magdy S. Abadir - Freescale Semiconductor Inc.
5.1 An Effective Guidance Strategy for Abstraction-Guided Simulation, F. Paula, A. Hu - Univ. of British Columbia5.2 Leveraging Semi Formal and Sequential Equivalence Techniques for Multimedia SoC Performance Validation, 
5.3 Synthesizing SVA Local Variables for Formal Verification, 
View Detail

Session: Leakage Power Analysis and Optimization
Type: Regular Session
Track: Low Power Design
Day:  Tuesday
Time: 2:00 PM - 4:00 PM
Room: 6B
Chair: Kanak Agarwal - IBM
6.1 Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization, D. Chiou, D. Juan, Y. Chen, S. Chang - Nat'l Tsing-Hua U.6.2 Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift, J. Seomun, J. Kim, Y. Shin - KAIST
6.3 Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation, J. Seomun, J. Kim, Y. Shin - KAIST
Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling, J. Seomun, J. Kim, Y. Shin - KAIST6.5s Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits, J. Seomun, J. Kim, Y. Shin - KAIST
View Detail

Session: PANEL: Making Manufacturing Work for You
Type: Panel
Track: DFM and the Manufacturing Interface
Day:  Tuesday
Time: 2:00 PM - 4:00 PM
Room: 6C
Chair: R. Puri - IBM
Organizers: S. Venkataraman - Intel
Speakers: 7.1 MFG Interface: Making Manufacturing Work for You, S. Griffith - Syntricity, B. Madge - LSI, W. Ng - Chartered, A. Oberai - Magma, G. Yeric - Synopsys, Y. Zorian - Virage, View Detail

Session: Energy and Performance Issues in On-Chip Communication Networks
Type: Regular Session
Track: System Level and Embedded
Day:  Tuesday
Time: 2:00 PM - 4:00 PM
Room: 6D
Chair: Robert Dick - Nothwestern Univ.
8.1 Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip, U. Ogras, R. Marculescu, P. Choudhary, D. Marculescu - CMU8.2 Introducing the SuperGT Network-on-Chip, A. Shacham, K. Bergman, L. Carloni - Columbia
8.3 Layered Switching for Networks on Chip, A. Shacham, K. Bergman, L. Carloni - Columbia
Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands, A. Shacham, K. Bergman, L. Carloni - Columbia8.5s The Case for Low-Power Photonic Networks on Chip, A. Shacham, K. Bergman, L. Carloni - Columbia
View Detail

Session: Circuit Simulation
Type: Regular Session
Track: Analog/Mixed-Signal/RF and Simulation
Day:  Tuesday
Time: 2:00 PM - 4:00 PM
Room: 6E
Chair: L. Miguel Silveira - INESC-ID
9.1 Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations., S. Srivastava, J. Roychowdhury - Univ. of Minnesota9.2 PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels, B. Yan, S. Tan, P. Liu - UC
9.3 Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis, B. Yan, S. Tan, P. Liu - UC
Simulating Improbable Events, B. Yan, S. Tan, P. Liu - UC9.5s SBPOR:Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits, B. Yan, S. Tan, P. Liu - UC
View Detail

Session: Signal and Power Delivery Integrity
Type: Regular Session
Track: Interconnect and Reliability
Day:  Tuesday
Time: 2:00 PM - 4:00 PM
Room: 6F
Chair: Eli Chiprout - Intel
10.1 On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise, M. Zhao, R. Panda, B. Reschke, Y. Fu - Freescale, T. Mewett - Australia Semiconductor, S. Chandraskearan, S. Sundareswaran, S. Yan - Freescale10.2 Optimal Selection of Voltage Regulator Modules in a Power Delivery Network, A. Roy, N. Mahmoud, M. Chowdhury - U. Illinois
10.3 Top-k Aggressors Sets in Delay Noise Analysis, A. Roy, N. Mahmoud, M. Chowdhury - U. Illinois
A New Twisted Differential Line Structure in Global Bus Design, A. Roy, N. Mahmoud, M. Chowdhury - U. Illinois10.5s Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew, A. Roy, N. Mahmoud, M. Chowdhury - U. Illinois
View Detail

Session: SPECIAL SESSION: Functional Verification of ESL Models
Type: Special Session
Track: Verification and Test
Day:  Tuesday
Time: 4:30 PM - 6:30 PM
Room: 6B
Chair: Robert B. Jones - Intel
11.1 Formal Techniques for SystemC Verification, M. Y. Vardi - Rice U.11.2 Design for Verification at System-Level and RTL, 
11.3 Verification Methodologies in a TLM-to-RTL Design Flow, 
Memory Modeling in ESL-RTL Equivalence Checking,  View Detail

Session: PANEL: Early Power-Aware Design and Validation: Myth or Reality?
Type: Panel
Track: Low Power Design
Day:  Tuesday
Time: 4:30 PM - 6:30 PM
Room: 6C
Chair: S. Bailey - Mentor
Organizers: G. Kamhi - Intel, S. Miller - ThinkBold
Speakers: 12.1 Early Power-Aware Design and Validation: Myth or Reality?, S. Curtis - Intel, J. Karmann - Infineon, S. Kosonocky - IBM, E. Macii - Politecnico di Torino, W. Nebel - OFFIS Research Institute, YC Wong - Broadcom, View Detail

Session: Memories in Embedded Systems
Type: Regular Session
Track: System Level and Embedded
Day:  Tuesday
Time: 4:30 PM - 6:30 PM
Room: 6D
Chair: Nigel Topham - U. Edinburgh
13.2 System for Coarse Grained Memory Protection In Tiny Embedded Processors, R. Rengaswamy, A. Singhania, A. Castner, E. Kohler, M. Srivastava - UC13.3 Reducing Off-Chip Memory Access Costs Using Data Recomputation in Embedded Chip Multi-processors, 
13.4s A Memory-Conscious Code Parallelization Scheme, 
A Self-Tuning Configurable Cache,  View Detail

Session: Statistical Techniques for Timing Analysis and Design
Type: Regular Session
Track: DFM and the Manufacturing Interface
Day:  Tuesday
Time: 4:30 PM - 6:30 PM
Room: 6E
Chair: Michael Orshansky - UT
14.1 Comparative Analysis of Conventional and Statistical Design Techniques, S. Burns, M. Ketkar, N. Menezes, K. Bowman, J. Tschanz, V. De - Intel14.2 Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction, 
14.3 NonLinear Statistical Static Timing Analysis for NonGaussian Variation Sources, 
Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting,  View Detail

Session: SPECIAL SESSION: WACI
Type: Special Session
Track: New and Emerging Technologies
Day:  Tuesday
Time: 4:30 PM - 6:30 PM
Room: 6F
Chair: L. Scheffer - Cadence
15.1s Chip Multi-Processor Generator, A. Solomatnikov, A. Firoozshahian, W. Qadeer, O. Shacham, Z. Asgar, K. Kelley, M. Wachs, R. Hameed, M. Horowitz - Stanford15.2s The Case for the Precision Timed (PRET) Machine, P. Gupta - Blaze, A. Kahng - UC San Diego, Y. Kim, S. Shah, D. Sylvester - U. Michigan
15.3s Quantum-Like Effects in Network-on-Chip Buffers Behavior, P. Gupta - Blaze, A. Kahng - UC San Diego, Y. Kim, S. Shah, D. Sylvester - U. Michigan
CAD-based Security, Cryptography, and Digital Rights Management, P. Gupta - Blaze, A. Kahng - UC San Diego, Y. Kim, S. Shah, D. Sylvester - U. Michigan15.5s Line End Shortening is not Always a Failure, P. Gupta - Blaze, A. Kahng - UC San Diego, Y. Kim, S. Shah, D. Sylvester - U. Michigan
15.6s You Can Get There From Here: Connectivity of Random Graphs on Grids, S. Levitan - U. Pittsburgh
15.7s High Performance and Low Power Electronics on Flexible Substrate, F. Gaffiot - Ecole Centrale de Lyon, J. Liu, I. O'Connor, D. Navarro
15.8 Novel CNTFET-based Reconfigurable Logic Gate Design, 
View Detail

Session: Distributed Computing: Automotive Network Design and Analysis
Type: Regular Session
Track: Automotive Theme
Day:  Wednesday
Time: 8:30 AM - 10:00 AM
Room: 6B
Chair: Antal Rajnak - Mentor.
16.1 Period Optimization for Hard Real-time Distributed Automotive Systems, A. Davare, Q. Zhu - UC, M. Natale - GM, C. Pinello - Cadence, S. Kanajan - GM, A. Sangiovanni-Vincentelli - UC16.2s Performance Analysis of FlexRay-based ECU Networks, 
16.3s Experimental Jitter Analysis in a FlexCAN Based Drive-by-Wire Automotive Application, 
Optimization of Static Task and Bus Access Schedules for Time-Triggered Distributed Embedded Systems with Model-Checking,  View Detail

Exh S M Tu W Th F #